Over time, SOI has become a popular design in field effect transistor (“FET”) technology. In prior years, the FET's large junction capacitance hindered its performance. For example, in NMOS transistors where doped N regions are embedded in silicon P substrates, depletion regions form in the substrate. These depletion regions are located at each area between the P and N regions (called a PN junction) and are characterized by a depleted number of majority carriers. Consequently, depletion regions must be charged with majority carriers before the NMOS can properly work. Recharging the depletion region with majority carriers can take so long that the time to charge the depletion region exceeds the time to switch the NMOS to the desired voltage. SOI rectifies this problem because it places a sheet of insulation between the P and N regions, thus eliminating the large depletion region and junction capacitance. Compared to a regular bulk transistor, SOI is advantageous to the extent it has low junction leakage, junction capacitance, and power consumption.
Nevertheless, SOI also has disadvantages. One drawback to the SOI structure is the floating body effect, which can degrade current flow. The floating body effect occurs when, at NMOS operation, electrons in the source terminal are drawn to a high electric field in the drain terminal and experience impact ionization. Impact ionization occurs when high speed carriers, like electrons, collide with atoms in a semiconductor lattice, like atoms in a drain. The impact ionization creates electron-hole pairs in the drain region. The low potential active Si bottom region draws these generated holes towards its bottom region. In a bulk transistor, the holes collecting at the Si bottom region exit through a low potential body contact. But, in an SOI structure, insulator separates the active Si region from the body. Therefore, without any body contact, generated holes collect at the active Si bottom and increase the potential of the active Si bottom. This creates a forward-bias between the source and the active Si bottom. As a result of the forward bias, electron injection occurs from the source to the active Si bottom. This, in turn, creates a parasitic NPN bipolar transistor junction, which lowers the threshold voltage and drain breakdown voltage of the NMOS.
An unmet need therefore exists for creating a body contact in a SOI structure that is useable as an exit for generated holes.